Pulse width modulators (PWMS) are a key circuit block in building power switching regulators. Digital dead-time controllers are circuit blocks converting the output from a pulse width modulator to two signals for driving a pair of complementary or quasi-complementary transistors, typically metal-oxide-semi-conductor field effect transistors (MOSFETs). In addition, dead-time delay gaps are inserted to eliminate possible “shoot-through” problems when both transistors conduct current simultaneously. A high level block diagram and timing waveform for a dead-time controller is illustrated in FIG. 15.
Dead-time delay gaps are normally set to small fractions of the pulse width modulator period. The values of these gaps are normally selected based on the turn-on/turn-off characteristics of the MOSFET transistors, recovery time of body diodes, difference between the input/output voltages of the switching power supply, parasitic capacitance at the MOSFET switching node, etc. In order to achieve maximum power efficiency over a wide range of loads, the two gaps must be accurately timed and, if possible, adjusted with an adaptive loop.
Conventional dead-time controllers employ resistor-capacitor networks or active devices to achieve time delay. To compensate for performance variations due to process-voltage-temperature (PVT) changes, on-chip calibration circuits are normally included. Digital dead-time controllers time all delay intervals with an accurate system clock, so no need for any distribute delay elements exists. The system clock is normally phase-locked to some timing reference to reduce sensitivity to PVT changes.
There is, therefore, a need in the art for an improved digital dead-time controller.